1. Field of the Invention
The present invention relates to an intermediate potential generating circuit, and more particularly relates to an intermediate potential generating circuit for producing an intermediate potential which is between a first potential and a second potential lower than the first potential, and outputting it to an output terminal.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as DRAM) is conventionally provided with an intermediate potential generating circuit for producing an intermediate potential Vcc/2 which is between a power supply potential Vcc and a ground potential GND. Intermediate potential Vcc/2 generated in the intermediate potential generating circuit is utilized as a precharge potential of a bit line and as a cell plate potential.
FIG. 3 is a circuit diagram showing a structure of a conventional intermediate potential generating circuit. With reference to FIG. 3, the intermediate potential generating circuit is provided with two reference potential generating circuits 31 and 36 and a drive circuit 41.
One reference potential generating circuit 31 includes a resistor element 32, N channel MOS transistors 33, 34 and a resistor element 35 that are serially connected between a line of power supply potential Vcc (hereinafter referred to as a power supply line) 20 and a line of ground potential GND (hereinafter referred to as a ground line) 21. Each of N channel MOS transistors 33 and 34 is diode-connected. Specifically, respective gates of N channel MOS transistors 33 and 34 are connected to their own drains. Resistor elements 32 and 35 have an equal resistance value and N channel MOS transistors 33 and 34 have an equal threshold voltage Vthn. Accordingly, an intermediate node N33 between N channel MOS transistors 33 and 34 is at intermediate potential Vcc/2, and an output node N32 between resistor element 32 and N channel MOS transistor 33 is at a first reference potential Vcc/2+Vthn.
The other reference potential generating circuit 36 includes a resistor element 37, P channel MOS transistors 38, 39 and a resistor element 40 that are serially connected between power supply line 20 and ground line 21. Respective gates of diode-connected P channel MOS transistors 38 and 39 are connected to their own drains. Resistor elements 37 and 40 have an equal resistance value and P channel MOS transistors 38 and 39 have an equal threshold voltage Vthp. Accordingly, an intermediate node N38 between P channel MOS transistors 38 and 39 is at intermediate potential Vcc/2, and an output node N39 between P channel MOS transistor 39 and resistor element 40 is at a second reference potential Vcc/2-Vthp.
Drive circuit 41 includes an N channel MOS transistor 42 and a P channel MOS transistor 43 connected in series between power supply line 20 and ground line 21. The gate of N channel MOS transistor 42 is connected to output node N32 of reference potential generating circuit 31 and the gate of P channel MOS transistor 43 is connected to output node N39 of reference potential generating circuit 36. A node N42 between MOS transistors 42 and 43 is an output node of the intermediate potential generating circuit.
An operation of this intermediate potential generating circuit will next be described. The output potential Vcc/2+Vthn of reference potential generating circuit 31 is supplied to the gate of N channel MOS transistor 42 of drive circuit 41, and the output potential Vcc/2-Vthp of reference potential generating circuit 36 is supplied to the gate of P channel MOS transistor 43 of drive circuit 41.
If a potential Vout of output node N42 is lower than intermediate potential Vcc/2, N channel MOS transistor 42 becomes conductive and output node N42 is charged. At this time, the potential of the gate of N channel MOS transistor 42 is Vcc/2+Vthn, so that output node N42 which is a source of N channel MOS transistor 42 is charged only to intermediate potential Vcc/2.
If potential Vout of output node N42 becomes higher than intermediate potential Vcc/2, P channel MOS transistor 43 becomes conductive and output node N42 is discharged. At this time, the potential of the gate of P channel MOS transistor 43 is Vcc/2-Vthp, so that output node N42 which is a source of P channel MOS transistor 43 is discharged only to intermediate potential Vcc/2. Therefore, potential Vout of output node N42 of the intermediate potential generating circuit is maintained at intermediate potential Vcc/2.
FIG. 4 is a circuit diagram showing a structure of another conventional intermediate potential generating circuit. Referring to FIG. 4, the intermediate potential generating circuit is provided with two reference potential generating circuits 51, 56 and a drive circuit 61.
One reference potential generating circuit 51 includes a P channel MOS transistor 52, an N channel MOS transistor 53, a P channel MOS transistor 54, and an N channel MOS transistor 55 connected in series between power supply line 20 and ground line 21. Each of N channel MOS transistors 53 and 55 is diode-connected. Respective gates of P channel MOS transistors 52 and 54 are connected to respective sources of N channel MOS transistors 53 and 55. Since gates of P channel MOS transistors 52 and 54 are respectively connected to nodes of low potential over N channel MOS transistors 53 and 55, each of P channel MOS transistors 52 and 54 operates as a resistor element. P channel MOS transistors 52 and 54 are identical in size, and N channel MOS transistors 53 and 55 have equal threshold voltage Vthn. Accordingly, an intermediate node N53 between N channel MOS transistor 53 and P channel MOS transistor 54 attains to intermediate potential Vcc/2, and an output node N52 between P channel MOS transistor 52 and N channel MOS transistor 53 attains to first reference potential Vcc/2+Vthn.
The other reference potential generating circuit 56 includes a P channel MOS transistor 57, an N channel MOS transistor 58, a P channel MOS transistor 59 and an N channel MOS transistor 60 connected in series between power supply line 20 and ground line 21. Each of P channel MOS transistors 57 and 59 is diode-connected. Respective gates of N channel MOS transistors 58 and 60 are connected to respective sources of P channel MOS transistors 57 and 59. The gates of N channel MOS transistors 58 and 60 are respectively connected to high potential nodes over P channel MOS transistors 57 and 59, so that each of N channel MOS transistors 58 and 60 operates as a resistor element. N channel MOS transistors 58 and 60 are identical in size, and P channel MOS transistors 57 and 59 have equal threshold voltage Vthp. Accordingly, an intermediate node N58 between N channel MOS transistor 58 and P channel MOS transistor 59 attains to intermediate potential Vcc/2, and an output node N59 between P channel MOS transistor 59 and N channel MOS transistor 60 attains to second reference potential Vcc/2-Vthp.
Drive circuit 61 is provided with an N channel MOS transistor 62 and a P channel MOS transistor 63 connected in series between power supply line 20 and ground line 21. The gate of N channel MOS transistor 62 is connected to output node N52 of reference potential generating circuit 51, and the gate of P channel MOS transistor 63 is connected to output node N59 of reference potential generating circuit 56. A node N62 between MOS transistors 62 and 63 is an output node of the intermediate potential generating circuit.
An operation of the intermediate potential generating circuit is described below. Output potential Vcc/2+Vthn of reference potential generating circuit 51 is supplied to the gate of N channel MOS transistor 62 of drive circuit 61, and output potential Vcc/2-Vthp of reference potential generating circuit 56 is supplied to the gate of P channel MOS transistor 63 of drive circuit 61.
If potential Vout of output node N62 becomes lower than intermediate potential Vcc/2, N channel MOS transistor 62 becomes conductive and output node N62 is charged up to intermediate potential Vcc/2. If potential Vout of output node N62 becomes higher than intermediate potential Vcc/2, P channel MOS transistor 63 becomes conductive and output node N62 is discharged up to intermediate potential Vcc/2. Accordingly, potential Vout of output node N62 of the intermediate potential generating circuit is maintained at intermediate potential Vcc/2.
FIG. 5 is a circuit diagram illustrating a structure of still another conventional intermediate potential generating circuit. With reference to FIG. 5, the intermediate potential generating circuit differs from that in FIG. 4 in that drive circuit 61 is substituted by a drive circuit 70.
Drive circuit 70 includes a P channel MOS transistor 71, an N channel MOS transistor 72, a P channel MOS transistor 73, and an N channel MOS transistor 74 connected in series between power supply line 20 and ground line 21, as well as a P channel MOS transistor 75 and an N channel MOS transistor 76 connected in series between power supply line 20 and ground line 21. The gate of N channel MOS transistor 72 is connected to output node N52 of reference potential generating circuit 51, and the gate of P channel MOS transistor 73 is connected to output node N59 of reference potential generating circuit 56. A node N72 between MOS transistors 72 and 73 is an output node of the intermediate potential generating circuit. Node N72 is connected to drains of MOS transistors 75 and 76.
Gates of P channel MOS transistors 71 and 75 are both connected to a drain of P channel MOS transistor 71, and P channel MOS transistors 71 and 75 thus constitute a current mirror circuit. Gates of N channel MOS transistors 74 and 76 are both connected to a drain of N channel MOS transistor 74, and N channel MOS transistors 74 and 76 thus constitute a current mirror circuit.
An operation of the intermediate potential generating circuit is next described. Output potential Vcc/2+Vthn of reference potential generating circuit 51 is supplied to the gate of N channel MOS transistor 72 in drive circuit 70, and output potential Vcc/2-Vthp of reference potential generating circuit 56 is supplied to the gate of P channel MOS transistor 73 in drive circuit 70.
If potential Vout of output node,N72 becomes lower than intermediate potential Vcc/2, N channel MOS transistor 72 becomes conductive and current is caused to flow from power supply line 20 to output node N72 through MOS transistors 71 and 72. At this time, since P channel MOS transistors 71 and 75 constitute the current mirror circuit, the electric current flowing from power supply line 20 through P channel MOS transistor 75 to output node N72 has a value corresponding to the value of the current flowing through P channel MOS transistor 71. Accordingly, potential Vout of output node N72 attains to intermediate potential Vcc/2 immediately.
On the other hand, if potential Vout of output node N72 becomes higher than intermediate potential Vcc/2, P channel MOS transistor 73 becomes conductive and electric current flows from output node N72 to ground line 21 through MOS transistors 73 and 74. At this time, N channel MOS transistors 74 and 76 constitute the current mirror circuit, so that the value of the electric current flowing from output node N72 through N channel MOS transistor 76 to ground line 21 has a value corresponding to that of the current flowing through N channel MOS transistor 74. Accordingly, potential Vout of output node N72 reaches intermediate potential Vcc/2 immediately. Potential Vout of output node N72 in the intermediate potential generating circuit is thus maintained at intermediate potential Vcc/2.
FIG. 6 is a circuit diagram showing a structure of a further conventional intermediate potential generating circuit. With reference to FIG. 6, the intermediate potential generating circuit differs from that shown in FIG. 3 in that reference potential generating circuit 36 is eliminated and drive circuit 41 is substituted by a drive circuit 81.
Drive circuit 81 is provided with two N channel MOS transistors 82 and 83 connected in series between power supply line 20 and ground line 21. The gate of N channel MOS transistor 82 is connected to output node N32 of reference potential generating circuit 31, and the gate of N channel MOS transistor 83 is connected to power supply line 20. A node N82 between N channel MOS transistors 82 and 83 is an output node of the intermediate potential generating circuit.
Next, an operation of the intermediate potential generating circuit is described. Output potential Vcc/2+Vthn of reference potential generating circuit 31 is supplied to the gate of N channel MOS transistor 82 in drive circuit 81. If potential Vout of output node N82 becomes lower than intermediate potential Vcc/2, N channel MOS transistor 82 becomes conductive and a charging current I82 flows from power supply line 20 to output node N82 through N channel MOS transistor 82. At this time, since the potential of the gate of N channel MOS transistor 82 is Vcc/2+Vthn, output node N82 which is a source of N channel MOS transistor 82 is charged only to intermediate potential Vcc/2.
In the meantime, since a discharging current I83 constantly flows from output node N82 through N channel MOS transistor 83 to ground line 21, potential Vout of output node N82 tends to decrease. Potential Vout of output node N82 is kept at intermediate potential Vcc/2, as discharging current I83 and charging current I82 are balanced.
However, the intermediate potential generating circuits shown in FIGS. 3 to 5 do not operate normally unless requirements of Vcc&gt;2 Vthn+2RI and Vcc&gt;2 Vthp+2RI are met (where R represents a resistance value of the resistor element in the reference potential generating circuit, and I represents a current value flowing in the reference potential generating circuit), since they are provided with reference potential generating circuits 31, 51 including diode-connected N channel MOS transistors 33, 34; 53, 55 as well as reference potential generating circuits 36, 56 including diode-connected P channel MOS transistors 38, 39; 57, 59.
On the other hand, supply voltage Vcc in a DRAM has been reduced in recent years, and threshold voltage Vthn and Vthp of the MOS transistors must be reduced in order to meet the requirements described above.
However, breakdown voltage characteristic is worse in the P channel MOS transistor compared to the N channel MOS transistor in the process technique now available, so that threshold voltage Vthp of the P channel MOS transistor cannot be reduced to the level corresponding to threshold voltage Vthn of the N channel MOS transistor. For this reason, the lowest value of supply voltage Vcc is determined by threshold voltage Vthp of the P channel MOS transistor in the intermediate potential generating circuits shown in FIGS. 3 to 5.
As for the intermediate potential generating circuit in FIG. 6, it is provided with only reference potential generating circuit 31 including diode-connected N channel MOS transistors 33 and 34. Therefore, it is sufficient to meet the requirement Vcc&gt;2 Vthn+2RI only. Therefore, reduction of supply voltage Vcc becomes possible, different from the intermediate potential generating circuits in FIGS. 3 to 5 in which the lowest value of supply voltage Vcc is determined by Vthp higher than Vthn.
However, the balance between charging current I82 and constantly flowing discharging current I83 cannot easily be maintained. In order to strike the balance, a circuit should be designed considering various factors such as supply voltage Vcc, temperature, and device property, and the circuit design becomes difficult.